1. Field of the Invention
This invention relates to an improved ECL OR/NOR gate circuit and, more particularly, refers to an ECL OR/NOR gate which employs a single load current source that is switched between the load current source transistors on the inverting and non-inverting output lines.
2. Discussion of Background and Prior Art
Emitter-coupled logic (ECL) is widely utilized in such diverse applications as instrumentation, computers, phased-array radar, telecommunications systems, and a host of modern electronics applications where high performance is required or desired. Fundamental curcuit design principles and fabrication processes for ECL are well known in the semiconductor art. See, e.g., Integrated Circuits Applications Handbook, ed. A. H. Seidman, Chp. 3, "Emitter Coupled Logic", pp. 55-94 (Wiley 1983); and D. A. Hodges et al Analysis and Design of Digital Integrated Circuits, pp. 271183 (McGraw-Hill 1983).
The basic building block for the design of ECL-based integrated circuits is a multiple input OR/NOR gate as shown in FIG. 1. Output line 18 which possesses an OR logic representation of the inputs A, B is driven by emitter-follower 13. When the input on the base of emitter-follower 13 is raised the output line 18 is pulled up or high, representing a digital "1". When the input on the base of emitter-follower 13 is lowered the output line 18 is pulled down by load current source transistor 11 and represents a digital "0". The state of conduction of reference transistor 17 controls emitter-follower 13 as the base of emitter-follower 13 is connected to the collector of reference transistor 17. In a similar manner output line 19 which possesses a NOR representation of the inputs A, B is driven by emitter-follower 12. Here, emitter-follower 12 is controlled by the state of conduction through either of input transistors 15 or 16. Emitter-follower 12 pulls NOR output line 19 up when its base is raised and load current source transistor 10 pulls NOR output line 19 down when the input on the base of emitter-follower 12 is lowered. The two emitter-followers 12 and 13 are never completely off since they set the respective logic levels. They simply conduct always to drive the associated output line to its appropriate voltage level. The bases of each of the two load current source transistors 10 and 11 are controlled by the bandgap reference voltage V.sub.CS, a stable, sometimes compensated reference voltage available on ECL integrated circuits. See A. H. Seidman, ed. Integrated Circuits Applications Handbook, pp. 498-499 (Wiley 1983); and D. A. Hodges et al, Analysis and Design of Digital Integrated Circuits, pp. 279-283 (McGraw-Hill 1983). Thus, in the normal operation of a conventional ECL OR/NOR gate circuit the two load current source transistors 10 and 11 are on at all times and draw a steady current. They serve to pull the output line down when the associated emitter-follower tends to turn off and keep the output line low until the associated emitter-follower tends to pull the output line up again. However, implicit in this method of operation is the fact that a given load current source transistor is on at times when it is serving no useful function. Thus, when an output line is intended to be high and is being pulled up by its emitter-follower the current draining through the associated load current source transistor works against the desired operation of the circuit and wastes power. This degrades the delay-power product, a standard measure of performance for ECL devices.
It is therefore an object of the present invention to provide a true complement ECL OR/NOR gate which uses less power.
It is an additional object of the present invention to provide an OR/NOR ECL gate in which a single current source is switched between the two load current source transistors on the respective output lines so that the majority of the current is being drawn by one or the other of the load current source transistors at a given time.
It is another object of the present invention to provide an OR/NOR ECL gate whose load current source transistors draw significant current only when they are pulling down the associated output line.